1. Field of the Invention
This invention relates to a packaging module for high density semiconductor chips. More particularly, the present invention relates to a thin film processing substrate embodied into a multichip hybrid module.
2. Description of the Prior Art
Integrated circuits are made very small in size to increase the speed operation of the devices and to reduce the cost of manufacture. The integrated circuit chips are provided with very small pads or exposed electrodes which are connected to larger and more stable circuit patterns or leads in a package. The leads are connected to pins which may be plugged into a printed circuit board.
One of the commercially successful packages or modules for housing integrated circuits is the dual inline package (DIP) which has two parallel rows of pins that may be plugged directly into a printed circuit board. As the number of active elements on the integrated circuit chips has been increased, there has been a corresponding increase in the requirement for the number of pins on the DIP modules to the point where problems are created with DIP modules when large scale integrated circuits (LSI) and very large integrated circuits (VLSI) are to be packaged. One of the main problems with the DIP module is that you cannot place the individual chips close enough together. When the chips cannot be placed close together, the circuits inside the module as well as the printed circuits outside of the module are so long as to create problems with delays.
Albert J. Blodgett, Jr. of IBM has suggested in an IEEE publication (see a Multilayer Ceramic Multichip Module; IEEE Transactions on Components from Hybrids and Manufacturing Technology, vol. 3, no. 4, December 1980, pages 633-637) that the interconnection density of a module can be increased through the use of a plurality of layers of ceramic substrates. This article describes a twenty-three layer ceramic substrate which includes power distribution layers, signal distribution layers and redistribution layers. The numerous ceramic layers are provided with thick film conductive patterns. Patterns on one or more surfaces are interconnected by vias between layers. When vias in adjacent layers are aligned, there is a connection between the aligned vias permitting interconnection between remote or adjacent patterns.
The multilayer ceramic module described above is first cast and then blanked in a green ceramic sheet form. The circuit pattern and metalization for the via holes is then applied to the green ceramic blank sheets which are stacked in a laminate and then sintered to join the circuit pattern on the various layers. Not only are there problems with the numerous layers which require precision alignment but the laminate must be sintered and completed before it can be tested to determine if there are any opens or breaks in the circuit patterns. Another problem with the above-mentioned multilayer ceramic substrate is that it requires eight pairs of X-Y wiring planes with interspersed impedence control layers.
The signal distribution lines of the multilayer ceramic module are made with thick film lines which are approximately five mils wide on the ceramic substrates which have a relative dielectric constant of approximately nine. For a fixed predetermined characteristic impedence, this high dielectric constant results in a higher line capacitance which is undesirable because it introduces excessive and undesirable signal delays.
Another undesirable effect of having the high relative dielectric constant is that it reduces the propagation speed of the signals.
Accordingly, it would be desirable to decrease the capacitance of the lines, to increase the speed of propagation of the signals in the signal distribution layers of a module, and to reduce the number of layers and complexity of the prior art modules.